In order for the e200z4d core to be able to access memory, a valid MMU TLB entry has to be created. TheSSCM does this automatically by reading the reset vector and modifying TLB entry 0 to create a 4 KBpage containing the reset vector address. The MMU VLE bit is set depending on the status of the VLE bitwithin the RCHW. The 4 KB MMU page must be 4 KB aligned. This means that the most efficient placeto put the application code is immediately after the boot sector. The 4 KB block provides sufficient spaceto:• Add MMU entries for SRAM and peripherals• Perform standard system initialisation tasks (initialise the SRAM, setup stack, copy constant data)• Transfer execution to RAM, re-define the flash memory MMU entry and transfer execution back to flash memory.Finally, the SSCM sets the e200z4d core instruction pointer to the reset vector address and starts the corerunning.